1. Field of the Invention
This invention is directed to 3 transistor Dynamic Random Access Memories (DRAMs), in general, and to multi-state DRAMs in particular which are embedded in a standard CMOS logic process.
2. Prior Art
FIG. 1. shows a schematic diagram of a three transistor dynamic memory cell similar to the one used by Intel and others in the late sixties and early seventies for computer memories. Two versions are shown: one in which the write data line 9 and the read data line 8 are separate (FIG. 1a) and one in which these two cell ports are common 6 (FIG. 1b). The three transistor dynamic memory cell uses a transistor Q1 3 as a write select device, Q2 2 as the read out buffer transistor whose gate serves as the storage capacitor, and Q3 1 as the read select device. Q3 1 is turned on by placing the read word line 7 in the high state or at Vdd and the write select transistor 3 is turned on by placing write word line 4 in the high state or at Vdd. The storage node is the gate capacitance of Q2 2. Since the right hand junction of Q1 3 will have leakage current, the charge stored on Q2's gate will bleed off over time and, therefore, periodic reading and re-writing or refreshing of cell will have to performed before the stored logic state of the cell is lost.
The one transistor/capacitor dynamic memory cell eventually replaced the three transistor cell by the mid seventies largely because of the superior density of the latter. The three transistor memory cell has one advantage over the one transistor/capacitor cell in that the three transistor cell produces a stable output current when read. The one transistor/capacitor cell basically outputs a voltage which is severely attenuated by the bit line capacitance (the voltage on the capacitor is reduced by roughly a factor of ten when read). For this reason, three transistor DRAM cells are still used in limited applications where memory density is not a factor such as data buffers.
The stable current output provided by the three transistor during read makes the cell a better candidate for multi-state data storage over the one transistor/capacitor cell.
As mentioned earlier, one very significant reason the one transistor/capacitor dynamic cell has become dominant is that special processing steps can be applied to the storage capacitor to make the cell very dense. This high density is achievable since the capacitor is readily amenable to vertical construction techniques unlike MOSFETs. Currently, stacked polysilicon layers or polysilicon blocks are used to make the capacitor which is placed over the select transistor or, alternatively, deep trench capacitors are used. Unfortunately, the process steps needed to make a compact dynamic memory cell are not compatible with logic processes. Generally speaking, dynamic RAM processes have one layer of metal and several layers of polysilicon whereas logic processes have one polysilicon layer and several metal layers. Thus, to add a one transistor/capacitor dynamic memory to a logic process requires the addition of several layers which drives up the chip cost considerably. It is only recently that chip companies have tried to "embed" dynamic memory cells into a logic chip. The chief driving force is the need for large, high data "bandwidth" memories in such applications as graphics processors. High data bandwidth can be achieved by using words with a large number of bits without having to worry about high pin counts as is the case when the memory and processor are separate chips.